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Preliminary
RT9256
Actively Alternative Mode Two-Phase / Dual Switching PWM Controller
General Description
The RT9256 is an analogous current mode design and is specifically promoted for high power density consideration platform with MLCC capacitor attached, such as high-end add-on graphic card core power and DDR SDRAM core power, etc. A highlight for RT9256 is the RichTek' s new innovation of actively alternative mode operation two-phase power conversion or dual PWM controller operation. Based on above innovation architecture, the RT9256 provides more flexibility and higher performance to customer application. The part is implemented specially for multiple power sourcing with power budget limitation. The part comes to small footprint package VQFN-32L 5x5.
Features
Analogous Current Mode Design Innovative Design for Actively Alternative Mode Operation : Two-Phase Power Conversion Dual PWM Controllers 2.5V to 12V Switching Source Power 0.8V to 3.3V Output Voltage Regulation Multiple Power Sourcing for Power Budget Limitation Adjustable VIN Feed-Forward Ramp Slope Adjustable Operation Frequency Precision Core Voltage Regulation Precision DCR Current Sensing (with High Quality Capacitor, X7R) 1% VREF Accuracy Input Voltage : 12V or 5V Bias Enable and PGOOD Function for SequencingConcerned Power Over Current Protection Over Voltage Protection External Soft Start Setting Operation Frequency Up to 1.0MHz Per Channel 32-Lead VQFN Package RoHS Compliant and 100% Lead (Pb)-Free
Ordering Information
RT9256 Package Type QV : VQFN-32L 5x5 (V-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
Note : Richtek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating.
Pin Configurations
(TOP VIEW)
UGATE1
25 24 23 22 21 20 19 33 18 17 9 10 11 12 13 14 15 16
PGOOD
27
Add-on graphic core power card DDR SDRAM core power Gaming Console High power density consideration platform Desktop/motherboard high power devices Power sequencing-concerned power application
32
31
30
VCC
RR1
SS1
Applications
CSN1 CSP1 COMP1 FB1 FB2 COMP2 CSP2 CSN2
1 2 3 4 5 6 7 8
29
28
BOOT1
26
IMAX1
VCC5
PHASE1 PGND LGATE1 PVCC PVCC LGATE2 PGND PHASE2
BOOT2
IMAX2
SS2
RR2
RT
VQFN-32L 5x5
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UGATE2
GND
EN
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5V to 12V
R7 10 R8 10 D1 SS0520
RT9256
12V
C1 1uF
29 VCC PVCC EN PGND RR1 SS1
C11 0.1uF
20/21 14 18/23 32 30
R9 180k
28
C2 1uF
Typical Application Circuit
VCC5 GND RR2
12 9
R1 180k 3.3V C3 to C6 47uFx4 Q3
NC 11 SS2 27 PGOOD NC 15 BOOT2 BOOT1 UGATE1 PHASE1 LGATE1 RT 22 13 R10 33k 24
Q2 09N03LT
12V
C12 0.1uF Q1 06N03LT L1 1uH C18 to C20 DCR 100uFx3 C13 to C16 22uFx4
26 25
Preliminary
16 UGATE2 17 PHASE2 19 LGATE2
DCR Q4 R3 3.9k 09N03LT R4 R5 180k VCC5
Figure 1. Two-Phase Application
L3 1uH 06N03LT R11 3.9k R12 1.8k
VOUT 1.2V/30A
C17 0.1uF
C7 to C9
100uFx3
C10 0.1uF
7 CSP2 1.8k 8 CSN2 5 FB2 COMP2 6
2 CSP1 1 CSN1 FB1 COMP1
4 R13 180k 3 IMAX1 31
R14 R15 22k 22k C21 820pF NC
R16 1k R17 2k
NC
10 IMAX2
R6 22k
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5V to 12V
D2 SS0520 D1 SS0520
DS9256-07 August 2007
12V
C1 1uF
29 VCC PVCC EN PGND RR1 SS1
C14 0.1uF R8 180k
20/21 14 18/23 32 30
28
C2 1uF
VCC5 GND RR2 SS2 PGOOD 27 NC BOOT1
C15 0.1uF
12 9
11
R1 180k C5 to C8 47uFx4 L3 1uH Q3 06N03LT C4 1uF C3 0.1uF
3V to 12V 15 BOOT2 16 UGATE2 UGATE1 PHASE1 LGATE1 RT CSP2 CSN2 5
NC
26 25 24 22 13 R9 33k 2 1
R10 1.8k Q1 06N03LT
3V to 12V
C15 to C18 22uFx4 L1 1uH DCR C20 to C22 100uFx3 Q2 09N03LT x2
Preliminary
Figure 2. Two-Switcher Application
17 PHASE2 19 LGATE2 7
R4 1.8k R3 3.9k Q4 09N03LT Q5 R14 3.9k
2.2V/15A
VOUT2
C10 to C12 100uFx3
DCR
VOUT1 1.2V/25A
C19 0.1uF
C13 0.1uF
8 FB2 COMP2
CSP1 CSN1 FB1 COMP1
R27 2.1k R5 180k
4 3 IMAX1 31
R11 180k NC
R16 1k R17 2k R13 22k R12 22k C23 820pF
R28 1.2k C14 820pF R7 22k R6 22k
6 10 IMAX2
RT9256
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RT9256
Function Block Diagram
VCC5
Preliminary
RT
OVP VCC GND SS2 Regulator
To PWM Logic
CLK1 VREF 2 Phase oscillator 50 to 1000kHz/phase CLK2 SS1 PGOOD EN
POR Soft Start & Power Good
UVP & Mode Select
FB2 COMP2 BOOT2 UGATE2 PHASE2 LGATE2 PVCC PGND CLK2 RR2 Ramp Current generator Driver
EA +
EA +
FB1 COMP1 Driver BOOT1 UGATE1 PHASE1 LGATE1 PVCC PGND Ramp Current generator CLK1 RR1
PWM Logic
+ PWMCP
+ PWMCP
PWM Logic
Current to Voltage Converter + +
Current to Voltage Converter + +
CSP2 CSN2
+
S/H
OCP
To PWM Logic
OCP
S/H
+
CSP1 CSN1
IMAX2
IMAX1
Operation
RT9256 is a highly flexible, high performance and high precision synchronous buck controller specifically designed for high-end graphic core power supply as well as DDR applications, with highly reduced external components and costs. RT9256 features two controllers that can be configured as a two-phase buck converter suitable for high power density applications like core power for GPU. It can also be configured as two independent buck converters for DDR power sets. RT9256 uses RichTek proprietary Analogous Current ModeTM topology which mimics the traditional peak current mode by sensing the valley current of the inductor via DCR sensing techniques and simulating the current ramp with an artificial ramp set externally. The Analogous Current Mode topology benefits all the advantages of peak current
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mode converter with much higher noise immunity than conventional one. Since the compensation is easier and with less constraint than that in voltage mode, using low ESR output capacitor as MLCC is possible, which therefore dramatically reduce the board size as well as the cost and has better transient response due to higher control bandwidth. RT9256 also adopts VIN feedfoward for ramp setting, which decreases the complexity for compensation by keeping the modulator gain constant along line variations. With the nature of current mode converter, current balance is automatically achieved in two-phase mode. By properly setting current sense resistors, current ratio other than 1 between two channels is also possible. RT9256 can also be used to form a single output voltage buck converter with dual input voltages.
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Preliminary
Out-of-phase switching in both two-phase and two-switcher modes reduces the input current ripple and therefore reduces the component requirement as well as cost. The wide input voltage range of the converter ranges from 3.3V to 12V. The output voltage can be set from 0.8V to 3.3V with external resistor divider. The bias voltage of the chip is VCC5. The IC integrates two control circuits for two synchronous buck converters. The default mode of RT9256 is two switcher mode. The two phase mode can be activated by pulling FB2 pin high before POR as shown in Figure 3.
POR
RT9256
The external elements selection of RT9256 includes 1: RT pin resister to GND to set the operation frequency of the chip. 2: CSN pin resister to set the current gain(ratio of inductance current IL and sensed current Ix) and current scaling in two phase mode operation. 3: RR pin resister to Vin to set the slope of the Vin feed forward ramp and the effective slope compensation of current mode. 4. IMAX pin resister to GND to set the over current level 5: capacitor at SS pin to set the soft-start time 6. type two compensation at COMP pin. Power on reset The POR circuitry monitors the supply voltage of the chip. When the chip power supply exceeds 4.2V, the chip releases the reset state and works according to the settings. Once the supply voltage is lower than 4.0V, POR circuitry resets the chip.
FB2
2PH
2SW
VIN detection The VIN detection circuitry monitors the switching power source when power up. As VIN > 1.8V, RR pin is enable for ramp setting and the chip is in ramp setting mode. The voltage at RR pin will be about 0.55V. Otherwise, the chip will be in VIN detection mode and RR pin is disable for ramp setting until VIN > 1.8V. In VIN detection mode, the UGATE and LGATE will be off and SS will be pulled low by a constant current of 10uA. The chip will enter the ramp setting mode and SS will re-softstart when VIN > 1.8V. In two switcher mode, the detection function work independently. In two phase mode, ramp setting mode will be activated when both channel' s VIN are ready. Enable
Figure 3 The power sequence of RT9256 includes: 1: POR function 2: VIN power supply detection 3: EN pin setting to enable the whole chip. 4: PG to indicate the power good condition of the chip The chip will detect the voltage at FB pin when SS pass Vcc5 - 1.3 and send a PG high signal if FB > 0.6V. The power sequence of the chip is shown in Figure 4.
EN
POR
VIN detection Vin > VCC5 - 1.3 SS
After POR reset, the chip monitors the voltage of EN pin. When VEN is higher than 0.8V, the chip is enabled. The chip is disabled when VEN is lower than 0.8V. With a precision threshold voltage, the EN pin can be used for power sequence.
SSH FB PG > 0.6V
Figure 4
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RT9256
Modes of operation
Preliminary
In two-phase mode, the single output control loop consists of one error amplifier shared with two pulse width modulators, two sets of current feed back components, two gate drivers and power components. The error amplifier at channel one with pins COMP1 and FB1 is used to control the pulse width modulator. The PWM signals of each channel are generated by comparison of the error amplifier output and the independent split-channel current ramp signals.
The default mode of RT9256 is two-switcher mode. Two buck controllers consisting of independent error amplifiers, PWM modulators, current sense amplifiers and ramp generators operate independently. The two-phase mode is activated by pulling FB2 high when POR. In two-phase mode, error amplifier of channel 1 performs the compensator of the converter for both channels. SS2 and COMP2 are also disabled in this mode. Soft-start A constant current of 10uA starts to charge the capacitor connected to SS pins right after the chip has been powered up and enabled. The ramp voltage on SS pins is also used to clamp the comp voltage during soft-start, which automatically constraints the output current due to the nature of current mode topology. This brings up smaller inrush current and smooth output voltage ramp. When the voltages on SS pins exceed VCC5-1.3V, the controller starts to monitor the voltage on FB pins. Once VFB is higher than 0.6V, the open drain PGOOD pin will be turned off, i.e. released indicating power good. The SS pins are also used as the timer during OCP and UVP hiccup. Frequency setting The converter switching frequency is programmed by connecting a resistor from the RT pin to GND. The frequency vs. R plot is shown in "Typical Operating Characteristics". Output voltage setting and control In two-switcher mode, both control loops consist of an independent error amplifier, a pulse width modulator, current feed back components, a gate driver and power components. The internal high accuracy bias provides the reference voltage of 0.8V at the non-inverting input of both error amplifiers. The output voltage is programmed by using a voltage divider at output and feeding the voltage division back to corresponding error amplifiers. As conventional current mode PWM controller, the output voltage is locked at the VREF of error amplifier and the error signal is used as the control signal of pulse width modulator. The PWM signals are generated by comparison of EA output and current ramp waves. Power stage transforms VIN to output by PWM signal on-time ratio.
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Preliminary Functional Pin Description
CSN1 (Pin 1), CSN2 (Pin 8) Current Sense Negative Input. These pins are negative input nodes of the current sense amplifiers used for DCR current sensing. Connect this pin with a resistor to the output node. CSP1 (Pin 2), CSP2 (Pin 7) Current Sense Positive Input. These pins are positive input nodes of the current sense amplifiers used for DCR current sensing. Connect this pin to the junction of the filter resistor and capacitor. COMP1 (Pin 3), COMP2 (Pin 6) Compensation Pin. In dual switching mode, these pins are output nodes of the error amplifiers. In two phase mode, only COMP1 is active. FB1 (Pin 4), FB2 (Pin 5) Feedback Pin. In dual-switching mode, these pins are negative input pins of the error amplifiers.When SS pass VCC5 - 1.3 and FB1 or FB2 < 0.6V, the UV protection function will be activated. The two-phase mode is activated by pulling FB2 above 4V when POR. The UV protection function will be enabled if FB1 < 0.6 when the SS pass VCC5 - 1.3. RR2 (Pin 9), RR1 (Pin 32) Ramp resistor. These pins are used to set the ramp voltages. Connecting a resistor from this pin to its converter input power sets the ramping slope of the control loop of the converter. Since it is connected to converter input power, the ramp slope is input-feed-forwarded. As VIN > 1.8V, RR pin is enable for ramp setting. IMAX2 (Pin 10), IMAX1 (Pin 31) Maximum Current Setting. These pins set the current limiting levels. Connect these pins with resistors to ground to set the current limit. SS2 (Pin 11), SS1 (Pin 30) Soft-start Pin. These pins provide soft-start function for their respective controllers. The COMP voltage of the converter follows the ramping voltage on the SS pin. RT (Pin 13)
RT9256
Timing Resistor. Connect a resistor from RT to GND to set the clock frequency. EN (Pin 14) Enable Pin. Pull the EN pin above 0.8V at POR (VCC5 > 4.2V), the whole chip function will be enabled. BOOT2 (Pin 15), BOOT1 (Pin 26) Bootstrap Power Pin. These pins power the high-side MOSFET drivers. Connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. Connect the anode of the bootstrap diode to the PVCC pin. UGATE2 (Pin 16), UGATE1 (Pin 25) Upper Gate Drive. These pins drive the gates of the highside MOSFETs. LGATE2 (Pin 19), LGATE1 (Pin 22) Lower Gate Drive. These pins drive the gates of the lowside MOSFETs. PHASE2 (Pin 17), PHASE1 (Pin 24) These pins are return nodes of the high-side drivers. Connect these pins to high-side MOSFET sources together with the low-side MOSFET drains and the inductor. GND (Pin 12) Chip Ground. PGND (Pin 18 and 23) Driver Ground. PVCC (Pin 20 and 21) Driver Power. VCC5 (Pin 28), VCC (Pin 29) The VCC5 pin is the internal 5.2V regulator output powered from the external voltage (VCC). VCC5 is dedicated for RT9256 internal use only and not for external power source.
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RT9256
PGOOD (Pin 27)
Preliminary
Power Good. In two-switcher mode, PGOOD is an open drain output used to indicate the status of the voltages on all SS pins, FB pins and VIN (by detecting RR at POR). PGOOD pulled low when 1. SS1 or SS2 < VCC5 - 1.3 2. FB1 or FB2 < 0.6V In two-phase mode (FB2 pulled high), PGOOD is an open drain output used to indicate the status of the voltages on SS1 pin and FB1 pin. PGOOD pulled low when 1. SS1 < VCC5 - 1.3 2. FB1 < 0.6V NC [Exposed Pad (33)] No Internal Connection.
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DS9256-07 August 2007
Preliminary Absolute Maximum Ratings
(Note 1)
RT9256
Supply Voltage --------------------------------------------------------------------------------------------------------- -0.3V to 16V Storage Temperature Range ---------------------------------------------------------------------------------------- -65C to 150C PHASE to GND DC ------------------------------------------------------------------------------------------------------------------------- -5V to 15V < 200ns ------------------------------------------------------------------------------------------------------------------ -10V to 30V BOOT to PHASE ------------------------------------------------------------------------------------------------------ 15V BOOT to GND DC ------------------------------------------------------------------------------------------------------------------------- -0.3V to VCC+15V < 200ns ------------------------------------------------------------------------------------------------------------------ -0.3V to 42V Input, Output or I/O Voltage ----------------------------------------------------------------------------------------- GND-0.3V to 7V Power Dissipation, PD @ TA = 25C VQFN-32L 5x5 --------------------------------------------------------------------------------------------------------- 1.923W Package Thermal Resistance (Note 4) VQFN-32L 5x5, JA ---------------------------------------------------------------------------------------------------- 52C/W Operation Junction Temperature Range -------------------------------------------------------------------------- -40C to 125C Junction Temperature ------------------------------------------------------------------------------------------------- 150C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 1.5kV MM (Machine Mode) -------------------------------------------------------------------------------------------------- 150V
Recommended Operating Conditions
(Note 3)
Supply Input Voltage -------------------------------------------------------------------------------------------------- 5V to 14V Junction Temperature Range ---------------------------------------------------------------------------------------- -20C to 70C
Electrical Characteristics
(VIN = 12V, TA = 25C, Unless Otherwise specification)
Parameter Supply Input Supply Voltage Power On Reset Power On Reset Hysteresis Enable Threshold Supply Current Soft Start Soft Start Current Oscillator Frequency Frequency Variation Frequency Range Maximum Duty Cycle Up-ramp setting pin On Hysteresis
Symbol VCC VCC5V VEN VEN ICC ISS
Test Condition
Min 4.5 4.0 0.1 0.75 20 3 8
Typ 12 4.2 0.3 0.8 50 5 10 300 -300 75 0.5
Max 14 4.4 0.5 0.85 100 10 15 330 10 1000 80 0.7
Units V V V V mV mA uA kHz % kHz % V
VCC =12V, VSS= 0V
FOSC
RT=33k RT= 5k to 50k Per phase Per phase RR = 120k
270 -10 50 70 0.3
VRR
To be continued
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RT9256
Parameter Reference Voltage Feedback Voltage Error Amplifier DC Gain Gain-Bandwidth Product Trans-conductance Maximum Output Current (source & sink) Current Sense GM Maximum Output Current (source) Gate Driver Maximum Upper Driver Source IUGATE Upper Driver Sink Lower Driver Sink Protection IMAX Voltage Under Voltage Protection Power Sequence Power Good Threshold Power Good Sink Capability VSS VIMAX VFB RUGATE RLGATE Maximum Lower Driver Source ILGATE IGM(MAX) GBW GM VFB Symbol
Preliminary
Test Condition Min Typ Max Units
0.792
0.8
0.808
V
70 CLOAD = 5pF RLOAD = 20k 6 630 300
88 10 660 360
-----
dB MHz uA/V uA
ICOMP(MAX) VCOMP=1/2 x VCC5
Rsense = 2k
90
--
--
uA
BOOT-PHASE = 12V VUGATE = 1V PVCC=12V VLGATE = 1V RIMAX = 15k
----0.95 0.55
1.3 3 1.5 1.5 1.0 0.60
-6 -3 1.05 0.65
A A V V V V
VSS pin rising IPGOOD = 4mA
VCC5-1.6 VCC5-1.3 VCC5-1 -0.05 0.2
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. JA is measured in the natural convection at TA = 25C on a high effective thermal conductivity test board of JEDEC 51-7 thermal measurement standard.
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Preliminary Typical Operating Characteristics
FB Voltage vs. Input Voltage
0.81
RT9256
FB Voltage vs. Output Current
0.82
VIN = VCC IOUT = 0A
VIN = VCC = 12V
0.805
0.81
FB Voltage (V)
FB Voltage (V)
0.8
0.8
0.795
0.79
0.79 5 6 7 8 9 10 11 12
0.78 0 2.5 5 7.5 10 12.5 15 17.5 20
Input Voltage (V)
Output Current (A)
Switching Frequency vs. RT Resistance
1200
Load Transient Response
IOUT = 0 to 20A
Switching Frequency (kHz)
1000 800 600 400 200 0 0 20 40 60 80 100
VOUT (50mV/Div) IL1 (5A/Div) IL2 (5A/Div)
Time (10us/Div)
RT Resistance (k ) (k)
Load Transient Response
IOUT = 20 to 0A IL1 (5A/Div)
Load Transient Response
IOUT = 0 to 20A
IL2 (5A/Div)
IL1 (10A/Div)
IL2 (10A/Div)
VOUT (50mV/Div)
VOUT (50mV/Div)
Time (10us/Div)
Time (200us/Div)
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RT9256
Turn On
Preliminary
Power Up
VIN = 12V IOUT = 20A
EN (5V/Div) PGOOD (5V/Div) VOUT (1V/Div) VOUT (500mV/Div) IL1 (10A/Div) IL2 (10A/Div)
SS1 (2V/Div)
Time (10ms/Div)
Time (2ms/Div)
Power Up
VOUT (1V/Div) VIN (10V/Div) PGOOD (5V/Div) SS1 (2V/Div) PGOOD (2V/Div) SS1 (2V/Div) VOUT (1V/Div) VIN = 12V IOUT = 20A VIN (2V/Div)
Power Off
VIN = 12V IOUT = 10A
Time (10ms/Div)
Time (100us/Div)
Dead Time
VIN = 12V IOUT = 10A UGATE1 (5V/Div) VIN = 12V IOUT = 10A
Dead Time
UGATE1 (5V/Div)
PHASE1 (5V/Div)
PHASE1 (5V/Div)
LGATE1 (5V/Div)
LGATE1 (5V/Div)
Time (20ns/Div)
Time (20ns/Div)
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DS9256-07 August 2007
Preliminary
RT9256
Dead Time
VIN = 5V IOUT = 10A UGATE1 (2V/Div)
Dead Time
VIN = 5V IOUT = 10A UGATE1 (2V/Div)
PHASE1 (2V/Div)
PHASE1 (2V/Div)
LGATE1 (2V/Div)
LGATE1 (2V/Div)
Time (20ns/Div)
Time (20ns/Div)
Turn On @OCP
VIN = 12V EN (5V/Div) UGATE1 (20V/Div) VIN = 12V
OCP
UGATE1 (20V/Div)
SS1 (2V/Div) V OUT (500mV/Div) V OUT (500mV/Div)
SS1 (2V/Div)
Time (20ms/Div)
Time (20ms/Div)
Ripple & Noise
VOUT (10mV/Div)
UGATE1 (10V/Div)
LGATE1 (10V/Div)
Time (1us/Div)
DS9256-07 August 2007
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RT9256
Application Information
Preliminary
VXSH = I XSH x 24k Where
0.5 (VIN - VOUT )TON DCR VOUT I XSH = IOUT - + x L R CSN R DC IOUT : output current
Current Sense, Ramp Setting, Current Balance and Current Scaling RT9256 senses the inductor current through inductor DCR and feeds the current signal back to the control loop. The current sensing circuitry, as in Figure 5 consists of an RC filter, a current sensing GM together with two external resistors. The current flowing the inductor as well as the DCR causes a ripple voltage proportional to inductor ripple current across the equivalent inductor DCR as in Figure 5, The ripple voltage can be obtained using an RC filter in parallel with the inductor, if the component values satisfy the following relationships.
L ESR DCR C
VIN : input voltage VOUT : output voltage L: inductance value TON : on time, TON = DxTs theoretically, D: duty cycle, Ts: switching clock period. The external resistor RR is used to sets the internal ramp voltage proportional to current. The simulated ramp voltage is also used to implement the slope compensation set together using a single resistor RR. The relationships between RR and the internal voltage ramp is: ( VIN - VOUT V DCR + k OUT ) 24k L L R CSN VIN - VRR / 64p RR R CSN V - VOUT V DCR / ( IN + k OUT ) / 64p L L 24k
+ GM -
CSP(Pin) RCSN RDC
=
CSN(Pin) IX
RR = (VIN - VRR ) x Where
Figure 5
L = ESR x C DCR
VRR: the voltage at RR pin to 0.55V RR : the resistance at RR pin k : the slope compensation coefficient, which is the ratio of the desired compensation slope to the down ramp slope. The ramp voltage is summed up with the sensed baseline voltage to form a complete current feedback signal. The simulated ramp signal is fed to the comparator of the PWM modulator, comparing with error amplifier output to generate PWM pulses. For two-phase mode with single input voltage and equal inductor currents, with the low offsets between internal sensing circuits built in RT9256 and the nature of current mode control loop, perfect current balance can be reached by simply using identical external components. For the applications in two-phase mode with single input voltage and unequal inductor currents, the valley current ratio between two channels are programmed by setting the ratio of the sensing resistors of these two channels. The relationship of the resistances and the current ratio is:
DS9256-07 August 2007
The current sense GM converts the voltage drop on the capacitor in the DCR sensing network together with the resistor RCSN connected from the VOUT to the CSN pin. RCSN defines the trans-conductance of the GM stage. An extra external resistor connected from RCSN to GND is recommended to offer the capability of sensing negative inductor current in applications where negative currents are possible at light load conditions. The sensed current Ix is: I x DCR VOUT , at steady state. IX = L + R CSN RDC IX = IL x DCR , provided RDC is left opened. R CSN
The valley of the sensed current Ix is sampled and held and converted to a DC voltage as a baseline of the current feedback ramp. The sampled and held baseline voltage converted from the sensed current is:
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Preliminary
IL1_VALLEY R CSN1 = IL2_VALLEY R CSN2
The ramp slope of both channels can be set the same. Note that using unequal currents will cause unequal modulator gain for different channels. Normally, if the current ratio is slightly deviated from 1, compensation should be taken care of for the channel with higher modulator gain, that is, the one with smaller current gain, in other words, the channel with higher current. However, if the current ratio is set too large, the channel with too much slope compensation will move its control loop towards voltage mode. In two-phase mode with dual input voltages and equal output currents, because the simulated ramp voltage is VIN feedforwarded in RT9256, typically by setting identical RR and RCSN for both channels, balanced modulator gains and inductor currents are automatically achieved. With larger difference in input voltages, the voltage at RR pin, which is around 0.55V, can be taken into considerations as previous calculations for the ramp settings. In two-phase mode with dual input voltages and unequal channel currents, the ramp setting is the same as that in dual-input, equal output currents conditions, and the current setting consideration is similar to that in single-input, unequal output currents conditions. Gate control a. Before SS signal reach the bottom of the ramp voltage, UGATE and LGATE will be off. b. If EN pin is pulled low UGATE and LGATE will be off. c. UV protection function caused by FB < 0.6V or VIN < 1.8V will activate the Vin detection mode. In Vin detection mode, the UG LG will be off and SS will be pulled low until ramp setting mode is activated. In two switcher mode, the detection function work independently. In two phase mode, ramp setting mode will be activated when both channel are ready. d. When OC function occurs and SS > VCC5 - 1.3, a constant current of 10A starts to discharge the capacitor connected to SS pin right away. When OC occurs, UGATE and LGATE will be off. When the voltage at the capacitor connected to SS pin pass about 0.4V, a constant current of 10uA starts to charge the capacitor.
DS9256-07 August 2007
RT9256
The PWM signal is enable to pass to UGATE and LGATE. In two switcher mode, OCP function is independent monitor. OCP function in two phase mode monitors both channels, either one can activate OCP. If the OC protection occurs three times, OCSD will be activated and shut down the chip. e. When fault conditions occur or SS < 0.4V, the current sense function will be disable. Power good PG = 1 when soft-start voltage >= (VCC5 - 1.3), and no fault conditions. a. In two-switcher mode, both channels' condition should satisfy. b. In two-phase mode, only are fault conditions related to SS2, FB2 omitted. Feedback Loop Compensation First, the ramp signal applied to the PWM comparator is proportional to the input voltage provided via the VIN pin. This keeps the modulator gain constant when the input voltage varies. Second, the inductance valley current proportional signal is derived from the voltage drop across the ESR of the inductance is added to the ramp signal. This effectively creates an internal current control loop. The resistor connected to the CSN pin sets the gain in the current feedback loop. The following expression estimates the required value of the current sense resistor depending on the maximum load current and the value of the inductance ESR. LESR RCSN = IMAX x 90 A Due to implemented current feedback, the modulator has a single pole response with -1 slope at a frequency determined by the load,
FPO = 1 2 x RO x CO
where RO is load resistance and CO is load capacitance. For this type of modulator, a Type 2 compensition circuit is usually sufficient. RT9256 is a simulated current mode buck converter using the high gain error amplifier with transconductance (OTA, Operational Transconductance Amplifier)
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RT9256
Preliminary
Pole and Zero : FP = 1 1 ; FZ = 2 x R1 x C2 2 x R1 x C1
Converter
The Transconductance IOUT GM = VM The mid - frequency gain. VOUT = IOUTZOUT = GMVINZOUT VOUT G= = GMZOUT VIN ZOUT is the shut impedance at the output node to ground (see Figure 6 and 7)
GM C1 R1
EA
Modulator
VOUT
FZ FPO FC
FP
C2
Figure 6. A Type 2 Error Amplifier with Shut Network to Ground
VOUT EA+ EA+ -
Figure 9. Feedback Loop Compensation Figure 9 shows the type two amplifier and its response along with the response of the current modulator and the converter. There is another type of compensation called type three compensation that adds a pole-zero pair to the type two network. As shown in Figure 10, adding a network between VOUT and VFB in addition to the original type two compensation can result in type three compensation. Figure 11 shows the difference of their AC response. Type three compensation has an additional pole-zero pair that causes a gain boost at the flat gain region. Pole and Zero : 1 1 FP = ; FZ = 2 x [R1//R2] x C 2 x R1 x C But the gain boosted is limited by the ratio (R1+R2)/R2.
GM
+ RO
Figure 7. Equivalent Circuit
Open Loop, Unloaded Gain
Gain (dB)
A
Closed Loop, Unloaded Gain
FZ
FP
Gain = GMP1 B
VOUT
Frequency (Hz)
R1 VFB R2
C
Figure 8. Gain Figure 8 shows a type two amplifier and its response along with a non-compensated one. The type two amplifier, in addition to the pole at origin, has a zero-pole pair that cause a flat gain region at frequency between the zero and pole
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Figure 10. Additional Network of Type Three Compensation Adding at VOUT and VFB
DS9256-07 August 2007
Preliminary
OCP
Pole Add type three compensation
RT9256
Zero Original type two compensation
Figure 11. AC Response Curve of Type Two and Three
C2
C1
R2
The RT9256 use cycle by cycle current comparison. The over current level is set by IMAX pin. When OC function occurs and SS > VCC5 - 1.3, a constant current of 10uA starts to discharge the capacitor connected to SS pin right away. When OC occurs UGATE and LGATE will be off. When the voltage at the capacitor connected to SS pin pass about 0.4V, a constant current of 10uA starts to charge the capacitor. The PWM signal is enable to pass to the UGATE and LGATE. In two switcher mode, OCP function is independent monitoring. OCP function in two phase mode monitors both channels, either one can activate OCP. If the OC protection occurs three times, OCSD will be activated and shut down the chip. RT9256 uses an external resistor RIMAX to set a programmable over current trip point. OCP comparator compares each inductor current with this reference current. RT9256 uses hiccup mode to eliminate fault detection of OCP or reduce output current when output is shorted to ground. VIMAX DCR x IL VCSN IX = + RIMAX R CSN RDC
OCP comparator IMAX IX + -
VIN
C3
R3
-
R1
+
VOUT
Figure 12. Type Three Compensation Network Type three compensation can also be done as shown in Figure 12. It has a pole at the origin, two poles, and two zeros. 1 1 Zero : FZ1 = ; FZ2 = 2 x [R1 + R3] x C3 2 x R2 x C1 1 1 Poles : FP1 = ; FP2 = 2 x R2 x C1 x C2 2 x R3 x C3 With small value of R3 and proper chosen poles-zeros, the gain boost will be less limited and obvious than that of the first kind of type three compensation.
Figure 13 UVP By detecting voltage at FB pin when SS > VCC5 - 1.3. If FB < 0.6, the chip will enter the VIN detection mode. In VIN detection mode, the UGATE and LGATE will be off and SS will be pulled low by a constant current of 10uA. A constant current oh 10uA starts to charge capacitor at SS pin when SS pass 0.4V. In two switcher mode, the detection function work independently. In two phase mode, ramp setting mode will be activated when both channel are ready. OTP Monitor the temperature near the driver part within the chip. Shutdown the chip when OTP.
Protection
VIN detection The VIN detection circuitry monitors the switching power source when power up. As VIN > 1.8V, RR pin is enable for ramp setting and the chip is in ramp setting mode. The voltage at RR pin will be about 0.55V. Otherwise, the chip will be in VIN detection mode and RR pin is disable for ramp setting until VIN > 1.8V. In VIN detection mode, the UGATE and LGATE will be off and SS will be pulled low by a constant current of 10uA. The chip will enter the ramp setting mode and SS will re-softstart when VIN > 1.8V. In two switcher mode, the detection function work independently. In two phase mode, ramp setting mode will be activated when both channel' s VIN are ready.
DS9256-07 August 2007
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RT9256
Outline Dimension
Preliminary
D
D2
SEE DETAIL A L
1
E
E2
e
b
1 2
1 2
A A1 A3
DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.
Symbol A A1 A3 b D D2 E E2 e L
Dimensions In Millimeters Min 0.800 0.000 0.175 0.180 4.950 3.400 4.950 3.400 0.500 0.350 0.450 Max 1.000 0.050 0.250 0.300 5.050 3.750 5.050 3.750
Dimensions In Inches Min 0.031 0.000 0.007 0.007 0.195 0.134 0.195 0.134 0.020 0.014 0.018 Max 0.039 0.002 0.010 0.012 0.199 0.148 0.199 0.148
V-Type 32L QFN 5x5 Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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DS9256-07 August 2007

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